1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a fin diode with increased junction area and methods for making same.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Diodes are another common device found in many integrated circuits.
In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. A so-called finFET device has a three-dimensional (3D) structure.
A fin topology also provides the potential of increased density for diode devices. However, as fin sizes decrease, the dopant implantation process can damage the tip portions of the fin, resulting in increased defects and reduced junction area. The aspect ratio of the fins also makes it difficult to implant dopants on the lower portions of the fin, which also reduces the junction area.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.